1. Field of the Invention
The present invention relates to a bistable flip-flop with reset control.
2. Discussion of the Related Art
D flip-flops produced by CMOS (complementary metal-oxide semiconductor technology customarily include a master stage and a slave stage which are clocked by offset clock signals. Each stage consists of a storage cell including two logic gates mounted in parallel, one of these two gates being feedback-mounted with respect to the other in order to provide for the storage function. In order to compensate for the leakage currents and thus provide for the stability of the stored information, the feedback-mounted logic gate is produced from resistive-channel MOS transistors, that is to say including a relatively long channel and a relatively long gate. These resistive-channel transistors occupy a sizeable area on an integrates circuit, and it is therefore generally sought to reduce their number in order to obtain the functionalities desired of a compact circuit.
The resetting of the D flip-flop must be performed simultaneously on the two stages on the basis of the same control signal. Conventionally, the master stage includes a NAND gate feedback-mounted with respect to an inverting gate, and the resetting of this master gate is provided for by one of the inputs of this NAND gate receiving the active reset control signal in the 0 state. This NAND gate requires four resistive-channel MOS transistors and is therefore relatively bulky in terms of integrated circuit area. Furthermore, this NAND gate must be supplemented with other logic elements intended to avoid write conflicts at the input of the inverting gate.